Currently, high-voltage devices typically have a relatively thick gate oxide layer to withstand high voltage. However, compared with the flat portion of the oxide layer formed on the active region, the oxide layer formed at a corner portion of the active region is relatively thin. This results in a higher electric field at the corner portion of the active region, and the field distribution is concentrated at the corner portion of the active region, thus reducing the reliability of a semiconductor device. In order to overcome the problems of an oxide layer at the corner of the active region that is thinner than the thickness of the oxide layer on a flat surface, current techniques generally increases the thickness of the gate oxide layer. However, such techniques have only limited effect in improving the oxide thickness at the corner of the active region.
In addition, in order to maintain maximum operating voltage, high-voltage devices also require a large isolation well region.